In a DDS generator the RAM address increment rate is determined from a fixed clock frequency by a digital block comprising a phase increment register and a phase accumulator.

The RAM is loaded with the amplitude values of the individual points of one cycle (360 degrees) of the desired waveform (e.g. a sinusoid). Typically the number of points used will be made equal to or greater than the number of vertical amplitude points.

Example for 12-bit system with a 4096 word waveform store, Fmax. of 40MHz & resolution of 0.0001Hz.

One complete cycle of the selected waveform is stored in RAM as 4096 12-bit amplitude values. As the RAM address is incremented the waveform values are output sequentially to the DAC which reconstructs the waveform as a series of voltage steps. Sinewaves and triangles are subsequently filtered to smooth the steps in the DAC output.

The frequency of the output waveform is determined by the rate at which the RAM addresses are changed; in a DDS system the address changes are generated as follows.

The RAM contains the amplitude values of all the individual points of 1 cycle (360°) of the waveform; each sequential address change corresponds to a phase increment of the waveform of 360°/4096. Instead of using a counter to generate sequential RAM addresses, a phase accumulator is used to increment the phase.

On each clock cycle the phase increment, which has been loaded into the phase increment register by the CPU, is added to the current result in the phase accumulator; the 12 most significant bits of the phase accumulator drive the RAM address lines. The output waveform frequency is now determined by the size of the phase increment at each clock. If each increment is the same size then the output frequency is constant; if it changes, the output frequency changes but with phase continuity.

The example uses a 40-bit accumulator and a clock frequency which is 2⁴⁰ x 10^-4 (~109·951MHz); this yields a frequency resolution (corresponding to the smallest phase increment) of Fclk/2⁴⁰ = 0·1mHz.

Only the 12 most significant bits of the phase accumulator are used to address the RAM. At a waveform frequency of Fclk/4096 (~27kHz) the RAM address increments on every clock. At all frequencies below this (i.e. at smaller phase increments) one or more addresses are output for more than one clock period because the phase increment is not big enough to step the address at every clock. Similarly at waveform frequencies above 27kHz the larger phase increment causes some addresses to be skipped, giving the effect of the stored waveform being ‘sampled’; different points will be sampled on successive cycles of the waveform.

The minimum number of points required to accurately reproduce a waveshape will determine the maximum useful output frequency: fmax = Fclk/No. of points. For sinewaves a suitably designed filter permits the waveform to be reproduced accurately towards the Nyquist limit (Fclk/2), although because of practical limitations to the filter performance, a lower limit may be set (e.g. 40MHz for a 110MHz clock).

For other waveforms, the required number of points depends upon the complexity of the waveform, the edge speed and transition speed, and the precision with which it must be reproduced.